Large scale integrated circuits (LSIs) are continually becoming increasingly complex with ever increasing numbers of circuit elements, such as transistors, passive elements, such as resistors and capacitors, and metal interconnections. Consequently, the overall size of complex LSI chips is increasing. This trend requires increasing accuracy in the lithographic processes that are employed to manufacture LSIs.
Typically, large scale integrated circuits are manufactured using a series of masks in lithographic processes to form successive patterns of materials on and regions in individual chips comprising a semiconductor wafer, thereby defining circuit elements of the chips. In the lithography process cycles, a semiconductor wafer is typically covered with a resist film that is responsive to incident energy. The resist film is selectively exposed to the energy in desired areas by projecting an energy beam through a mask or by direct irradiation of the resist film with the energy beam. When a mask is used, the mask includes energy transmissive and non-transmissive portions forming a pattern to transmit the incident energy selectively and thereby produce a desired image on the resist film. The resist film changes in its chemical characteristics in response to exposure to the incident energy beam that is transmitted through the mask. Following the selective exposure to the incident energy, the resist film is developed, leaving in place parts of the resist film that have been exposed (or that have not been exposed depending upon the characteristic of the resist film) to the incident energy beam. The remaining parts of the resist film cover underlying areas of the substrate so that subsequent processes can be carried out in selected areas of the semiconductor wafer. These processes include etching, ion implantation, metallization, and so forth. In direct irradiation of a resist film, for example, by an electron beam without a mask, the energy beam is directed across the resist film in a predetermined pattern to expose the resist film selectively. Subsequent processing using the exposed resist film is the same as when the resist film is exposed through a mask.
In the traditional lithography processes used in integrated circuit processing and in other applications, the energy-responsive resist film exposed through a mask has been a photoresist film that is responsive to light, including visible light and/or ultraviolet light. Ultraviolet light, with its shorter wavelength, permits improved resolution of the images formed on the resist film so that smaller features can be formed as compared to resist films responsive to visible light. More recently developed techniques employ resist films that are sensitive to the energies associated with electron beams and x-rays, permitting still further resolution improvements and reduction in the sizes of the images formed on the resist films. Currently, these advanced techniques permit the formation of images as small as a few tenths of micrometers.
With expected increases in LSI complexity and the inclusion of larger numbers of circuit elements on a single chip, still smaller images will have to be formed on chips and the chips will have a larger size. For example, a dynamic random access memory (DRAM) having a one megabit capacity currently formed on a single chip requires the reproduction of lithographic images having dimensions as small as about one micrometer. A DRAM with a one Gigabit capacity, even if produced on a very large chip, for example, thirty millimeters by thirty millimeters, is projected to require minimum lithographic image dimensions of about two hundred nanometers. In order to manufacture LSIs using images that are so small with a reasonable yield, the placement accuracy of the features on a semiconductor wafer must be measurable to at least tens of nanometers and preferably less than ten nanometers.
The metrological accuracy, i.e., less than ten nanometers, required to produce integrated circuits having the expected future integration density can presently be achieved with optical apparatus available at only a few locations in the world, i.e., national laboratories, such as The National Institute of Standards and Technology (NIST) in Gaithersburg, Md., and a few very large corporations. The cost of including such a capability in a semiconductor wafer fabrication facility is currently very high. That cost could ultimately prevent progress in the production of ever more highly integrated LSIs. Optical measurement of the placement accuracy of artifacts on a substrate produced lithographically, with or without a mask, to accuracies of about fifty nanometers consumes substantial amounts of time, for example, one week per substrate. That long delay in confirming the accuracy of a mask is not compatible with an LSI manufacturing environment in which hundreds of masks may be prepared each day. Accordingly, continued development of metrology techniques for improving the accuracy of measurements of the positions of artifacts formed lithographically, including by photolithography, electron beam lithography, and x-ray beam lithography, at reasonable cost must be developed to promote continued progress in the semiconductor device integrated circuit arts.
One technique that has been developed in recent years for determining the relative position of one artifact on a substrate relative to other artifacts on a substrate with a high degree of accuracy without the use of optical instruments employs a voltage-dividing potentiometer. A voltage-dividing potentiometer is formed from an electrically conducting layer on a substrate. The potentiometer includes includes a bridge for conducting current and multiple taps that extend from the bridge for measuring the division of voltages along the bridge. A voltage-dividing potentiometer is shown in concept in FIG. 1. There, a bridge 1 has a current I flowing through it. Taps 2, 3, and 4 are in contact with the bridge 1 and extend transverse to it at various locations along the bridge 1. The end taps 3 and 4 are separated by a length L. The center tap 2 is centrally disposed between the end taps 3 and 4. Generally, the center line of the center tap 2 is offset from the midpoint of the length L by a distance x. The voltage V.sub.1 between taps 2 and 3 and the voltage V.sub.2 between taps 2 and 4 are both measured. From those measurements, assuming the uniformity of the bridge 1, the offset of the center tap 2 from the midpoint between the end taps 3 and 4 can be determined. The measurements are entirely electrical and no optical apparatus is required to make the positional determinations.
This voltage-dividing potentiometer technique has been applied in various forms to semiconductor wafers in order to determine the position of an electrically conductive artifact with respect to two other electrically conductive artifacts, for example, the end taps. Schematic examples of the geometry of several voltage-dividing potentiometers that have been tested for use in semiconductor device processing applications are illustrated in FIG. 2. In each of the four examples, current is conducted through a bridge while voltages are measured between pairs of taps extending from the bridge. The taps each include a probing pad and the bridge includes two pads. The pads are contacted mechanically by respective electrical probes for supplying current to the bridge and for measuring the voltage differences between pairs of taps.
The voltage-dividing potentiometer technique has important practical and economic advantages. With a voltage-dividing potentiometer, the position of a center tap relative to the center position between two end taps can be determined simply by electrical measurements. No optical instrument having a resolution on the order of ten nanometers is required to make measurements to an accuracy of one hundred nanometers or better. In practice, voltage-dividing potentiometers can be formed lithographically on any substrate bearing an electrically conducting film. After formation, the potentiometer is subjected to probing, i.e., the contacting of probes to the various pads, and evaluation of the measured voltages to determine the relative positioning of the electrically conducting taps formed by lithography. Electrical test equipment for probing the pads of a voltage-dividing potentiometer and evaluating the measured voltages is far less expensive than an optical instrument providing the same measurement accuracy (e.g., $250,000 versus $5,000,000). As LSI technology progresses toward more complex circuitry with smaller circuit elements, the cost advantage electrical determination of artifact position over optical determination should increase.
In older applications of the potentiometer technique, the bridge between the two end taps of a voltage-dividing potentiometer is long relative to the widths of the bridge and of the taps. However, as the length of the bridge has become shorter, for example, ten micrometers, for measurements in smaller areas of a substrate, that length has become comparable to the widths of the bridge and taps, for example, one to two micrometers. These dimensional relationships affect the voltage measurements made with a potentiometer. Substantial research into the effects of taps of widths comparable to the bridge length has shown that the relatively wide taps shorten the effective length of the bridge between the end taps. This research demonstrated that the voltage-dividing potentiometer measurements can be corrected to provide accurate position results using a term .delta.L that accounts for the effective shortening of the bridge length when the taps have finite widths relative to the bridge length. This correction eliminates the restriction on the minimum size of a voltage-dividing potentiometer that can be used to make reliable position measurements electrically.
In addition, it was determined in the research that the shape of the "corners" where the taps contact or intersect the bridge affects voltage-dividing potentiometer results when the potentiometers are small relative to the widths of the bridge and the taps. When those corners lack a particular symmetry, taps on opposite sides of the bridge may have different .delta.L correction terms, increasing the complexity of interpreting potentiometer measurements. This reported research showed that by placing the end and center taps on the same side of a bridge, the center-to-center spacing between a center tap and the end taps of a single potentiometer can be determined electrically with a residual error below ten nanometers.
The foregoing research concerning voltage-dividing potentiometers is reported in Cresswell et al "A Modified Sliding Wire Potentiometer Test Structure For Mapping Nanometer-Level Distances", Proceedings of IEEE 1991 International Conference on Microelectronic Test Structures, pages 129-134 (1991); Allen et al, "Elimination Of Effects Due To Patterning Imperfections In Electrical Test Structures For Submicrometer Feature Metrology", Solid-State Electronics, Volume 35, pages 435-442 (1992); Allen et al, "Voltage-Dividing Potentiometer Enhancements For High-Precision Feature Placement Metrology", Proceedings of IEEE 1992 International Conference on Microelectronic Test Structures, pages 174-179 (1992), and Allen et al, "A New Test Structure For The Electrical Measurement Of The Width Of Short Features With Arbitrarily Wide Voltage Taps", IEEE Electron Device Letters, Volume 33, pages 322-324 (1992). These publications are each incorporated herein by reference.
While the voltage-dividing potentiometer provides a simple means for electrical measurement the position of an electrically conducting artifact on a substrate, the sensitivity of the measurement declines when the spacing between artifacts, e.g., end and center taps, reaches distances on the order of one millimeter and greater, for example, across spans on large chips and particularly near opposite edges of a DRAM chip thirty millimeters by thirty millimeters in size. Optical measurements are effective in determining the positions of images that are widely spaced on a substrate. However, as already discussed, the cost of the optical measurement apparatus is very high and the time required to measure one substrate is very long. The substantial delay required to confirm mask accuracy before placing the tested sample and similarly prepared masks into production is incompatible with efficient LSI manufacturing operations.
Accordingly, it would be desirable to provide a method of and articles for measuring the relative positions of relatively widely spaced electrically conducting artifacts on a substrate to an accuracy of ten nanometers or better using an electrical technique, such as the voltage-dividing potentiometer technique, that can be carried out quickly at a wafer fabrication and mask manufacturing site at relatively low cost using lithography tools and electrical test apparatus present at the wafer fabrication site.